With the advent of the broadband technique and high-speed transmission rate in recent years, deterioration in the transmission waveform in serial signal transmission has become of a serious problem. The function of pre-emphasis is a technique of emphasizing the amplitude of a transmission signal at the time of transition thereof on a transmission side, in order to prevent pattern-dependent deterioration of the transmission signal, thereby improving a waveform of the signal on a receiving side. In the transmission at the rate on the order of GHz, in which the log of signal attenuation due to skin effect and dielectric losses per unit distance of a transmission line increases in proportion to the log of the frequency of signal, the application of pre-emphasis is crucial and indispensable.
With the pre-emphasis, the signal level during the time the pre-emphasis is operating differs from that during the time the pre-emphasis is not operating. Thus, with increase in the operating frequency, the difference in delay presents itself as jitter, such that the eye opening becomes does not satisfies ultimately the specification. It is therefore necessary to take appropriate measures to reduce jitter during the time of employing the pre-emphasis function.
As an output buffer circuit with a small propagation delay time, having a pre-emphasis function, which is operable at a lower voltage and which is suited for high speed operation, there is disclosed in Patent Document 1 a configuration shown herein in FIG. 9. The configuration shown in FIG. 9 includes a first buffer B1 and a second buffer B2. The first buffer B1 includes a first P-channel field effect transistor P1, which has a source electrode connected to a high potential power supply VDD, and a first N-channel field effect transistor N1 which has a source electrode connected to a low potential power supply VSS. The second buffer B2, includes a second P-channel field effect transistor P2, which has a source electrode connected to the high potential power supply VDD, and a second N-channel field effect transistor N2, which has a source electrode connected to the low potential power supply VSS. The driving power of the first P-channel field effect transistor P1 is set so as to be larger than that of the second N-channel field effect transistor N2, while the driving power of the first N-channel field effect transistor N1 is set so as to be larger than that of the second P-channel field effect transistor P2. In FIG. 9, L denotes a transmission line, the beginning end of which is connected to an output terminal TOUT of the buffer circuit and the terminal end of which is connected to a receiving terminal TRV on the receiving end. Rt denotes a termination resistor.
FIG. 11 shows instances of an input signal and an output signal for the output buffer circuit of FIG. 9. It may be seen that, in FIG. 9, a current bit signal SO1 of FIG. 11 is supplied to a terminal TA, whilst an inverted pre-bit signal SO2 is supplied to a terminal TB. The inverted pre-bit signal SO2 is obtained on inverting the current bit signal SO1 and on shifting the signal by one bit. When the signals SO1, SO2 are supplied to the terminals TA and TB, respectively, an output waveform, shown as an output signal SOUT in FIG. 11, is obtained at the output terminal TOUT of the output buffer circuit. If the bits of the signals SO1, SO2 are (1,1) or (0,0), the output signal SOUT is at a Voh1 level or Vol1 level, respectively, whereas, if the bits of the signals SO1, SO2 are (1,0) or (0,1), the output signal SOUT is at a Voh2 level or Vol2 level, respectively. Only when the current bit signal is changed from 0 to 1 or from 1 to 0, such change is emphasized in one bit period by the output signal SOUT, such that decrease in signal caused by loss on the transmission line is pre-emphasized on a driver side (output buffer side) to send out the signal. When the current bit signal is changed from 0 to 1, the transition from the level Vol2 to the level Vol1 (>Voh2) occurs, by way of pre-emphasis, whereas, when the current bit signal SO1 is changed from 1 to 0, the transition from the level Voh2 to the level Vol1 (<Vol2) occurs, by way of pre-emphasis.
FIG. 10 shows an alternative configuration, disclosed in Patent Document 1. In an output buffer B20 in this alternative configuration, in distinction from the configuration shown in FIG. 9, a P-channel field effect transistor P3 is connected across the source electrode of the P-channel field effect transistor P2 and the high potential power supply VDD, whilst an N-channel field effect transistor N3 is connected across the source electrode of the N-channel field effect transistor N2 and the low potential power supply VSS. A signal from a terminal TS is inverted by an inverter INV3 and thence supplied to the gate electrode of the P-channel field effect transistor P3, and a signal from the terminal TS is supplied to the gate electrode of the N-channel field effect transistor N3 to provide the output buffer B20 with a on/off switching control function.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-94365A (FIGS. 1 and 4)